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MM74HC4020 * MM74HC4040 14-Stage Binary Counter * 12-Stage Binary Counter
February 1984 Revised February 1999
MM74HC4020 * MM74HC4040 14-Stage Binary Counter * 12-Stage Binary Counter
General Description
The MM74HC4020, MM74HC4040, are high speed binary ripple carry counters. These counters are implemented utilizing advanced silicon-gate CMOS technology to achieve speed performance similar to LS-TTL logic while retaining the low power and high noise immunity of CMOS. The MM74HC4020 is a 14 stage counter and the MM74HC4040 is a 12-stage counter. Both devices are incremented on the falling edge (negative transition) of the input clock, and all their outputs are reset to a low level by applying a logical high on their reset input. These devices are pin equivalent to the CD4020 and CD4040 respectively. All inputs are protected from damage due to static discharge by protection diodes to VCC and ground.
Features
s Typical propagation delay: 16 ns s Wide operating voltage range: 2-6V s Low input current: 1 A maximum s Low quiescent current: 80 A maximum (74HC Series) s Output drive capability: 10 LS-TTL loads
Ordering Code:
Order Number MM74HC4020M MM74HC4020SJ MM74HC4020MTC MM74HC4020N MM74HC4040M MM74HC4040SJ MM74HC4040MTC MM74HC4040N Package Number M16A M16D MTC16 N16E M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
MM74HC4020
MM74HC4040
(c) 1999 Fairchild Semiconductor Corporation
DS005216.prf
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MM74HC4020 * MM74HC4040
Logic Diagrams
MM74HC4020
MM74HC4040
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MM74HC4020 * MM74HC4040
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (ICD) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns -40 +85 C 2 0 Max 6 VCC Units V V
Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage
(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 .26 .26 0.1 8.0 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 Units V V V V V V V V V V V V V V V V A A
Conditions
VIN = VIH or VIL |IOUT| 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA 4.5V 6.0V 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT| 4.0 mA |IOUT| 5.2 mA 4.5V 6.0V 6.0V 6.0V
VOL
Maximum LOW Level Output Voltage
VIN = VIH or VIL |IOUT| 20 A
IIN ICC
Maximum Input Current Maximum Quiescent Supply Current
VIN = VCC or GND VIN = VCC or GND IOUT = 0 A
Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC4020 * MM74HC4040
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL tREM tW Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q Maximum Propagation Delay Reset to any Q Minimum Reset Removal Time Minimum Pulse Width 10 16 ns
Note 5: Typical Propagation delay time to any output can be calculated using: tP = 17 + 12(N-1) ns; where N is the number of the output, QW, at VCC = 5V.
Conditions
Typ 50
Guaranteed Limit 30 35 40 20
Units MHz ns ns ns
(Note 5)
17 16 10
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay Clock to Q1 TPHL, tPLH Maximum Propagation Delay Between Stages from Qn to Qn+1 tPHL Maximum Propagation Delay Reset to any Q (4020 and 4040) tREM Minimum Reset Removal Time tW Minimum Pulse Width Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V tTLH, tTHL Maximum Output Rise and Fall Time tr, tf Maximum Input Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 6) Maximum Input Capacitance
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC.
TA = 25C Typ 10 40 50 80 21 18 80 18 15 72 24 20 6 30 35 210 42 36 125 25 21 240 48 41 100 20 16 90 16 14 30 10 9 75 15 13 1000 500 400
TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 5 24 28 265 53 45 156 31 26 302 60 51 126 25 21 100 20 18 95 19 16 1000 500 400 4 20 24 313 63 53 188 38 31 358 72 61 149 50 25 120 24 20 110 22 19 1000 500 400
Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
2.0V 4.5V 6.0V
(per package)
55 5 10 10 10
pF
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MM74HC4020 * MM74HC4040
Timing Diagram
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MM74HC4020 * MM74HC4040
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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MM74HC4020 * MM74HC4040
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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MM74HC4020 * MM74HC4040 14-Stage Binary Counter * 12-Stage Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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